The present disclosure relates to a semiconductor device, more particularly to a semiconductor device that includes a vertical gate-all-around transistor (VGAA) and a planar transistor.
A VGAA transistor includes a channel that extends in a vertical direction and that interconnects a source and a drain thereof, a gate oxide that surrounds the channel, and a gate that surrounds the gate oxide. The VGAA transistor may be implemented in a semiconductor device as a core transistor for forming a logic circuit, or as an input/output (I/O) transistor for forming an I/O circuit coupled electrically to external circuits.
When used as an I/O transistor, the gate oxide of the VGAA I/O transistor is made thick in order to sustain a high voltage, e.g., an electrostatic discharge (ESD)-induced voltage, applied thereto by the external circuits. However, the VGAA I/O transistor is still susceptible to ESD-induced damages.
When used as a core transistor, the gate oxide of the VGAA core transistor is made thin in order to increase a gate input capacitance thereof. However, the VGAA core transistor still has an insufficient gate input capacitance.